A Custom Bus Macro Generator for Fpga Dynamic Partial Reconfiguration
نویسنده
چکیده
This work aims to improve the Caronte Hardware Architecture by introducing a new kind of Bus Macro, called Custom Bus Macro, instead of the Xilinx Bus Macro currently used. Such new hardware architecture is called YaRA, Yet another Reconfigurable Architecture, and actually represents an open DRESD research topic. The main benefits introduced by this Custom Bus Macro are design facilitation and the possibility of go on with all possible communications during an area reconfiguration (Obviously communications that involve this area are excluded).
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